Synchronous Counter

A synchronous counter, in contrast to an asynchronous counter, is one whose output bits change state simultaneously, with no ripple. The only way we can build such a counter circuit from J-K flip-flops is to connect all the clock inputs together, so that each and every flip-flop receives the exact same clock pulse at the exact same time:

In synchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel). The circuit below is a 3-bit synchronous counter. The J and K inputs of FF0 are connected to HIGH. FF1 has its J and K inputs connected to the output of FF0, and the J and K inputs of FF2 are connected to the output of an AND gate that is fed by the outputs of FF0 and FF1.

Asynchronous (ripple) counter

An asynchronous (ripple) counter is a single d-type flip-flop,
 with its J (data) input fed from its own inverted output. This circuit 
can store one bit, and hence can count from zero to one before it 
overflows (starts over from 0). This counter will increment once for 
every clock cycle and takes two clock cycles to overflow, so every cycle
 it will alternate between a transition from 0 to 1 and a transition 
from 1 to 0. Notice that this creates a new clock with a 50% duty cycle
 at exactly half the frequency of the input clock. If this output is 
then used as the clock signal for a similarly arranged D flip-flop 
(remembering to invert the output to the input), one will get another 1 
bit counter that counts half as fast. Putting them together yields a 
two-bit counter: